1. Field of the Invention
The present invention generally relates to the design and testing of integrated circuits, and more particularly to a method and system for testing an array of a large number of electronic devices such as transistors formed on an integrated circuit for statistical characterization.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements grouped to perform a logic function. Cell types include, for example, core cells, scan cells and input/output (I/O) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
Faster performance and predictability of responses are elements of interest in integrated circuit design. As process technology scales to the deep-submicron (DSM) regime, it is becoming increasingly important for the performance and reliability of IC chips and systems to understand how variations in process parameters affect the operation of an electronic device or circuit. In particular a designer needs to model responses such as current flow or capacitance with changes in voltage (I-V and C-V curves) for transistors, and resistance/capacitance measurements for wiring. Device testing may further include leakage measurements across a gate, to indirectly assess the quality of an oxide material and identify potential flaws like pin holes or edge defects. Some devices such as static random-access memory (SRAM) require testing the memory elements with random fluctuations in threshold voltages to better characterize the circuit. Devices should also be stress tested, i.e., under different conditions such as varying temperatures.
It is additionally useful to understand how spatial variations (e.g., devices located in different dies on a single wafer) can be affected by process parameters. Conventional testing systems provide for the measurement of some process parameters using an array having a large number of the same devices for statistical characterization purposes. These systems have for example transistors arranged in addressable rows and columns. Selector control logic allows parameters of interest such as voltage or current to be injected at a desired device under test (DUT) node, and the outputs of the DUTs are routed through appropriate selectors to a measurement unit.
Circuit designers make assumptions about spatial variations of parameters which have a significant impact on product performance, but there is often no reliable system for verifying these assumptions. While the some test structures provide a fair basis to generally characterize the response of the devices, the measurements are not completely accurate since they fail to take into consideration various effects on signal creation and transmission. Even metal wires have a very small resistance (as well as capacitance) that affects the propagation of signals in the wires. These loading effects can vary with wire length and environmental parameters such as temperature. Calibration of the measurement circuitry does not compensate for variations in the loading effects. Moreover, spatial variability in integrated circuits is becoming worse due to variations such as Leff variation, doping concentrations, spurious leakage, systematic variation due to chemical mechanical planarization, etc. Existing test structures cannot adequately account for the variability in these measurements. In order to reliably characterize the variabilities, hundreds of samples are needed, which is even more impractical given the limited number of input/output (C4) pads provided on the circuits. Prior art test systems mostly provide only a few transistors on the kerf structure to monitor long-distance variabilities (wafer-to-wafer or die-to-die).
One test system which provides superior measurement of current/voltage response (I-V) is disclosed in U.S. patent application Ser. No. 11/422,913 filed Jun. 8, 2006, which is hereby incorporated. FIG. 1 illustrates one embodiment of that invention. The test circuit 2 includes a plurality of transistors (DUTs) 4 arranged in rows and columns, with each column being driven at its top and its bottom by four driver/clamps (two for the gate line and two for the drain line). Each driver/clamp has three voltage lines: a clamp input, a drive input, and a sense output. The driver/clamps are selectively controlled by level-sensitive scan design (LSSD) latches which are set by the test software. The sense signal from a driver/clamp provides a high impedance output which can be used to measure the voltage being applied at the top or bottom end of the column. The sense output is used to calibrate the drive or clamp signals, and can be used to dynamically monitor those signals and compensate for voltage strength variations by using the sense signal as an input to a feedback loop that adjusts the power supply for the drive or clamp voltages. Another set of LSSD latches on the left side acts as a current steering circuit to selectively direct the current from the row of the selected DUT to a measuring pin, while the currents of the remaining (non-selected) rows are directed to a sink pin. These steering devices lie in series between the source terminal of the DUT and electrical ground, causing the row voltages to rise slightly above ground. The parasitic resistance of the wire also adds an additional resistance between the source node of the DUT and the steering device. To account for these resistive voltage (IR) drops, sense capability is added to measure the row voltages at both ends of the array.
The current steering in this prior test circuit 10 is advantageous because the sense voltage at the right side may be used as a measure of the exact voltage appearing at the source node of the selected DUT. This current steering allows the measurement of extremely low currents (for example, gate leakage) of a DUT embedded in an array of devices. The difference between the sense voltages at the two ends of a row can further be used as an indicator of the IR drop due to parasitic resistances. Thus any voltage measurement for the device under test may be calibrated by deriving the difference between the sensed voltages at the left and right ends of the selected row and providing this difference to the measurement unit.
While the system of FIG. 1 is useful for characterizing the I-V response of a device, it does not provide any capacitance measurements and in particular does not yield any capacitance/voltage (C-V) relationships. The correlation between I-V and C-V curves for a device can provide significant insight into the root causes of variability and can be used to build a better variability device model. There are methods for measuring capacitance parameters but they suffer from certain limitations and disadvantages.
For front-end of line (FEOL) testing, i.e., at the device level, capacitance is measured using a standard instrument such as a Keithley Model 950 analyzer. That analyzer measures capacitance versus voltage as well as capacitance versus time characteristics of semiconductor devices using a direct-current (DC) bias and a small alternating-current (AC) signal measurement. These types of instruments suffer inaccuracies due to parasitic capacitances, and elaborate procedures must be followed to minimize the parasitic effects. This instrument is also unsuitable for testing of large arrays of devices.
For back-end of line (BEOL) testing, i.e., at the interconnect level, capacitance measurement is charge-based. See, e.g., the article “A Simple Method for On-Chip Sub-Femto-Farad Interconnect Capacitance Measurement” by B. McGaughy et al., IEEE Electron Device Letters, vol. 18, no. 1 (January 1997). In that method two non-overlapping AC signals are sent along two identical wire branches that gate current to an output node where capacitance is measured. The difference in capacitance measured with each signal is adjusted based on the signal frequency and magnitude to yield the BEOL capacitance. This technique requires careful timing of the AC signals as well as precise matching between the two wire branches.
Capacitance can alternatively be measured using coupling effects as explained in the article “Crosstalk-Based Capacitance Measurements: Theory and Applications” by L. Vendrame et al., IEEE Trans. on Semiconductor Mfg., vol. 19, no. 1 (February 2006). According to that method cross-coupling capacitances are extracted by measuring crosstalk currents. This technique similarly requires careful signal timing, and has poor accuracy if the capacitor used in the test has any leakage. It is also unsuitable for testing of large arrays of devices.
As a further disadvantage, none of the foregoing techniques can be implemented in a circuit that also allows I-V testing of the same devices. It would, therefore, be desirable to devise an improved testing structure which could accurately measure the capacitances of devices in a large test array. It would be further advantageous if the same testing structure could be used to evaluate I-V curves for the DUTs.